3.1. Channel Design Methodology

To demonstrate how to successfully manage the design challenges that high-speed channel design presents, this chapter describes the proven design process and methodology used for the Rambus^® Direct RDRAM^® and XDR™ channels ^[1][2][3][4]. The channel design and modeling methodology is, in essence, the process of balancing device and system characteristics with architectural constraints. This process enables the creation of component and channel specifications that guarantee the system operation, at the intended frequency, over all processing ranges and operating conditions. It is important to realize that not all SI engineers have the opportunity to define an I/O interface from the ground up. The typical case is that a standard-setting body defines the signaling methods and specifications. Sometimes, that body only defines a part of the system, as is often the case for memory interfaces, where only memory specifications are explicitly provided. Understanding how the standards are derived is very useful in performing trade-off analysis. The following discussion assumes that one has an option to define and design an I/O interface.

The Rambus channel design methodology considers system-level effects as key elements of the overall device and system requirements and specifications. We apply a top-down methodology, whereby the system-level specifications drive the component-level specifications, as illustrated in Figure 3.2. SI engineers work with architectural engineers to define the system requirements in the first step. Next, we perform the first-order analysis, where we create channel models, based on the extrapolated historical design and data. In the third step, we attempt to identify critical channel parameters, based on the proposed signaling topology and methods. We analyze these critical parameters to evaluate their impact on system performance and the design goals. After we are satisfied with the design, we proceed to the fourth step, which is to create a more detailed channel (signal integrity) model and power integrity model. We then use these models to define the initial specifications for various channel components, including the Tx and Rx parameters. These specifications define the I/O silicon/circuit design.