10.5. Summary

Accurate modeling of the clock is crucial for modern high-speed link analysis, because jitter contributed by the clocking circuitry is one of the most dominant components. A brute-force method of budgeting for clocking jitter, without considering clock to data jitter tracking, often leads to pessimistic results. This chapter presents a generalized formulation that can be applied to model any clocking topology. It also shows how to derive specific formula for common serial interfaces (for example, SerDes and PCIe systems), as well as memory interfaces (for example, DDR3/GDDR5/Mobile XDR systems). Furthermore, the chapter describes the key parameters for each clocking topology and presents models for both CDR and jitter amplification due to passive channel ISI.

Finally, a few key points from this chapter: