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Signal-integrity analysis has evolved greatly over the last two decades, reaching beyond traditional passive-channel analysis. Previously, driver and receiver performance dominated link performance. However, as data rates continue to increase, link performance is limited more by noise and jitter than intrinsic transistor performance. As the interface speed increases, the noise and jitter (due to the device, channel, and power distribution network) start to interact with each other. This interaction makes analyzing link performance a challenging task, and a common topic for both circuit designers and SI engineers. Often, SI engineers focus on high-frequency modeling and simulation of passive channels: They lack a system-level or circuit-level design perspective. This chapter presents a basic introduction to system-level issues and various noise sources in high-speed link designs.