16.2. Capturing Signal Waveforms

Capturing signal waveforms using on-chip measurement circuitry is challenging, because it requires a sub-sampling technique using high-bandwidth samplers ^{[8][9][10][11]}. Modern I/O designs often utilize the maximum transistor bandwidth to send data, so implementing a sub-sampling circuit could take significant power and silicon area overhead. Consequently, although sub-sampling techniques can be implemented in test vehicles, they are not suitable for production chips. A simpler version of the sub-sampling circuit, based on an additional adaptive sampler, is used for serial link designs [1] ^[12], and the same version (without the adaptive sampler) is implemented in memory interfaces [2].

In [2], a waveform is indirectly captured by measuring the BER using a technique similar to the technique described in the previous section. The only additional hardware required is a masking feature, used to select an error at a particular bit location. The basic principle is illustrated using a simple step as the input. First, the input pattern ...000111... is sent repeatedly. Then, the 2-D BER maps are measured for each bit location. Figure 16.3 demonstrates the 2-D BER maps for the pre-transition and post-transition bits, respectively. In this example, the error locations are mapped by comparing the received data to 1. By tracking the location with the error probability of 0.5, the signal waveform can be traced. To locate the 0.5 error location, the voltage offset is shmooed, as described in the previous section. Because the error rate of 0.5 is considered, knowing the correct bit value is not necessary. In a real implementation, the shmoo process can be optimized to track only near the 0.5-bit error probability line, instead of sweeping the entire voltage range. To filter out jitter due to random noise an averaging scheme can be used, or the measurement curve can be fitted with smooth functions. The overall process is summarized in Figure 16.4.