15.5. Summary

Substrate noise is the next challenge, following power supply noise, to budgeting, designing, and analyzing high-speed interfaces. This chapter discusses substrate noise and its jitter impact on high-speed I/O interfaces.

The chapter first discusses the substrate modeling methodology, including both DC and high-frequency approaches. The chapter also presents an on-chip substrate noise-measurement structure (noise monitor) and implements its prototype with a low-power memory controller PHY interface. The autocorrelation-based measurement methodology greatly reduces the bandwidth requirement, which would otherwise be challenging to meet, using direct time-domain measurement techniques. The noise monitor achieves the voltage resolution of finer than 150μV, and a measurement bandwidth of at least 10GHz. Measuring the PHY’s self-induced substrate noise verifies that it is not very significant in this stand-alone low-power PHY test chip environment. Additionally, the SNIJ sensitivity is characterized (aided by the implemented substrate noise generator), and observed consistent sensitivity results on two DQ links in the test chip. The on-chip measurement structure is proven useful in investigating the substrate noise and its impact. Self-contained and compact in size, it serves as a vital tool for further in-depth study of the impact of substrate noise jitter on the high-speed and low-power I/O interfaces for the future.