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14.4. Case Study

Two examples are discussed in this section to illustrate the analysis of power supply noise and its jitter impact in high-speed I/O interfaces. The first example discusses the supply noise analysis and jitter sensitivity analysis for a high-speed SerDes system with comparison between simulation results and measurement data [8]. The second example focuses on correlation of the net PSIJ impact between the prediction and measurement data on a high-speed memory controller interface operating at 6.4Gbps.

14.4.1. Supply Noise in High-Speed SerDes System

This section provides an analysis of the on-chip power-supply noise characteristics using the test system, shown in Figure 14.13. The interface is a serial-to-serial transceiver delivering high bandwidth point-to-point interconnections across system backplanes at data rates of up to 6.4Gb/s. It integrates eight bi-directional serial links, each operating at a data rate of up to 6.4Gb/s. Additionally, it contains Data Route Logic to control the data flow traffic between the different links, and Control Logic, which contains general logic for the initialization of the links, as well as logic used for characterization (for example, pattern generators). Four separate on-chip supply domains are used for different circuit blocks inside the test system. The sensitive timing-control circuits (for example, PLLs) are supplied by VDDA. All the circuits inside the eight link slices are supplied by VDD, except for the channel termination resistors, which are supplied by VTT. This case study focuses on VDD and VDDA, because they are the major sources of system jitter. The on-chip supply-noise-measurement circuits are integrated onto the interface test chip for the purposes of correlation. Chapter 16, “On-Chip Link Measurement Techniques,” covers the details of these circuits.


  

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