5.5. On-Chip Wire Modeling

As I/O speed continues to increase, even on-chip routings start to exhibit transmission-line effects. This section discusses the transmission line modeling of on-chip interconnects. Traditionally, on-chip global nets are modeled using RC or RLC networks. Due to the highly lossy nature of on-chip wires, circuit engineers insert a buffer to account for loss and to minimize a delay due to the RC network. However, buffers are subject to power-supply noise, and minimizing the number of buffers is desirable. In a high-speed I/O interface, modeling the global clock net is more important than the core area, because the I/O clock frequency is often much higher than the core clock frequency. Modern I/O interfaces operate at multi-gigahertz data rates that will soon reach 10Gb/s in future designs. This will require routing the 5GHz clock signal net over the interface area, which often covers the entire die side of the processor. On the other hand, the core frequency remains relatively constant due to peak power consumption, and chip performance is increased by using multi-cores. With high frequency I/O clock nets, on-chip wires can no longer be modeled using simple lumped RC models; transmission line models or distributed RLGC models are preferable ^{[46] [47] [48]}.

In addition to the high frequency nature of the I/O clock, each segment of clock wires for the I/O interface is relatively long when compared to core clock wires. This is because a smaller number of repeater buffers is used for I/O to minimize the buffer jitter induced by power-supply noise. For low-power applications, the LC resonance tank is considered as a clock distribution ^[49]. This resonant circuitry saves power consumption by eliminating the need for buffers. The importance of accurately modeling the clock wires is even more pronounced for this application, because the wire inductance becomes a part of the LC resonance tank. The on-chip modeling method presented by Qi, et al. ^[50] was originally developed to model clock wires for the LC resonance tank, but it can be applied to other general on-chip clock wires. This section reviews the on-chip wire modeling method described by Qi, et al. [50].