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13: Architecture of 8085 > 13.5 WAIT STATE GENERATION

images 13.5 WAIT STATE GENERATION

The present day memory and peripheral chips are fast enough for a 8085 working at 3 MHz. So wait states are generally not needed at all. If 8085AH-2 is used, which can work at 5 MHz, there may be a need to insert one wait state, between T2 and T3. The circuit shown in Fig. 13.20 easily achieves this.

The circuit uses two D-type positive edge-triggeredflip flops, with active low Reset inputs. At the beginning of T1, ALE goeshigh and causes Q1 to go high. As Q1 and D2 are connected, D2 remains highthroughout T1. The positive edge of T2 clock causes Q2* to become 0. This is connected to ready input of 8085. Thus, ready input remains 0 throughout the T2 state. So 8085 enters Twait, instead of T3, after T2. Also, when Q2* becomes 0, Reset1* becomes 0, thus making Q1 output as 0 throughout T2 state. The positive edge of Twait causes Q2* to become 1. This makes ready input as 1, andso after Twait state, 8085 enters the T3 state. Thus, one wait state is inserted by the circuit in Fig. 13.20 between T2 and T3. This can be visualized from the waveforms indicated in Fig. 13.21.


  

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