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Chapter 1. Introduction > Levels of Abstraction in VLSI Testing

1.4. Levels of Abstraction in VLSI Testing

In the design hierarchy, a higher level description has fewer implementation details but more explicit functional information than a lower level description. As described in Section 1.2.1.1, the various levels of abstraction include behavioral (architecture), register-transfer, logical (gate), and physical (transistor) levels. The hierarchical design process lends itself to hierarchical test development, but the fault models described in the previous section are more appropriate for particular levels of abstraction. In this section, we discuss test generation and the use of fault models at these various levels of abstraction.

1.4.1. Register-Transfer Level and Behavioral Level

The demand for CAD tools for the design of digital circuits at high levels of abstraction has led to the development of synthesis and simulation technologies. The methodology in common practice today is to design, simulate, and synthesize application-specific integrated circuits (ASICs) of millions of gates at the RTL. So-called “black boxes” or intellectual property (IP) cores are often incorporated in VLSI design, especially in SOC design, for which there may be very little, if any, structural information. Traditional automatic test pattern generation (ATPG) tools cannot effectively handle designs employing blocks for which the implementation detail is either unknown or subject to change; however, several approaches to test pattern generation at the RTL have been proposed. Most of these approaches are able to generate test patterns of good quality, sometimes comparable to gate-level ATPG tools. It is the lack of general applicability that prevents these approaches from being widely accepted. Although some experimental results have shown that RTL fault coverage can be quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library, it is unrealistic to expect that stuck-at fault coverage at the RTL will be as high as at the gate level [Min 2002].


  

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