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Acknowledgments

The authors wish to thank Prof. Duncan M. (Hank) Walker of Texas A&M University for contributing a portion of the Delay Testing section; Prof. Mehrdad Nourani of the University of Texas at Dallas for contributing to the Signal Integrity and Power Supply Noise section; T.M. Mak of Intel Corp. for contributing to the Soft Errors, Fault Tolerance, and Defect and Error Tolerance sections; Prof. Charles Stroud of Auburn University for contributing to the FPGA Testing section; T.M. Mak of Intel Corp. and Dr. Mike Peng Li of Wavecrest Corp. for contributing to the High-Speed I/O Testing section; and Dr. Soumendu Bhattacharya and Prof. Abhijit Chatterjee of the Georgia Institute of Technology for contributing to the RF Testing section; as well as Teresa Chang and her lovely daughter Alice Yu of SynTest Technologies for typing the text and drawing the figures.


  

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