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Verification Techniques for System-Level Design

Verification Techniques for System-Level Design

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Contents

The Morgan Kaufmann Series in Systems on Silicon

Acknowledgments

Ch. 1. Introduction

Ch. 2. Higher-Level Design Methodology and Associated Verification Problems

Issues in High-Level Design

C/C++-Based Design and Specification Languages

System-Level Design Methodology Based on C/C++-Based Design and Specification Languages

Verification Problems in High-Level Designs

Ch. 3. Basic Technology for Formal Verification

Ch. 4. Verification Algorithms for FSM Models

Ch. 5. Static Checking of Higher-Level Design Descriptions

Ch. 6. Equivalence Checking on Higher-Level Design Descriptions

Ch. 7. Model Checking on Higher-Level Design Descriptions

Ch. 8. Simulation-Based Verification Techniques for System-Level Designs

Ch. 9. Conclusion

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Chapter 2. Higher-Level Design Methodology and Associated Verification Problems

Issues in High-Level Design

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