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System-on-Chip Test Architectures: Nanometer Design for Testability
By: Laung-Terng Wang; Charles Stroud; Nur Touba
Publisher: Morgan Kaufmann
Pub. Date: November 20, 2007
Print ISBN-10: 0-12-373973-X
Print ISBN-13: 978-0-12-373973-5
eISBN-10: 0-08-055680-9
eISBN-13: 978-0-08-055680-2
Pages in Print Edition: 896
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Overview
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
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Engineering > Electrical Engineering
Electrical Engineering > Semiconductor Technology
