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14.4. DFT-Assisted Testing

Testing methods described in previous sections work well for characterization-level testing, but they have several distinct disadvantages for high volume manufacturing test. For high-volume manufacturing test, typical testing of the I/O interfaces on an ATE requires it to match the performance of the DUT’s I/O. I/O data rates can range from 1 GHz for parallel buses and more than 6 Gbps for serial links. ATE that meet these requirements cost quite a lot; in addition, test time and test programming complexities often mean delayed time-to-market. This combination can result in high product cost that may make the product noncompetitive. This becomes a problem when mass-market personal computers and consumer digital appliances increase their performance bandwidth and both high-speed parallel and serial I/O interfaces become the norm.

These trends and costs have motivated ways to test these products on mainstream test platforms (e.g., digital VLSI tester) with reasonable test time. There have been two trends: (1) making changes to the loadboard, and (2) incorporating I/O-specific DFT into the design. We refer to these test methods as DFT-assisted testing in which the DFT circuits are embedded on the loadboard or within the silicon itself. With this approach, no new or special equipment has to be purchased and time-to-market and product cost will fit into the business of mass marketing these technologies into the hands of consumers.


  

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