System-on-Chip Test Architectures: Nanometer Design for Testability > Software-Based Self-Testing

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System-on-Chip Test Architectures: Nanometer Design for Testability

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The Morgan Kaufmann Series in Systems on Silicon

Ch. 2. Digital Test Architectures

Ch. 3. Fault-Tolerant Design

Ch. 4. System/Network-on-Chip Test Architectures

Ch. 5. SIP Test Architectures

Ch. 6. Delay Testing

Ch. 7. Low-Power Testing

Ch. 8. Coping with Physical Failures, Soft Errors, and Reliability Issues

Ch. 9. Design for Manufacturability and Yield

Ch. 10. Design for Debug and Diagnosis

Ch. 11. Software-Based Self-Testing

About This Chapter

Introduction

Software-Based Self-Testing Paradigm

Processor Functional Fault Self-Testing

Processor Structural Fault Self-Testing

Processor Self-Diagnosis

Testing Global Interconnect

Testing Nonprogrammable Cores

Instruction-Level DFT

DSP-Based Analog/Mixed-Signal Component Testing

Ch. 12. Field Programmable Gate Array Testing

Ch. 13. MEMS Testing

Ch. 14. High-Speed I/O Interfaces

Ch. 15. Analog and Mixed-Signal Test Architectures

Ch. 16. RF Testing

Ch. 17. Testing Aspects of Nanotechnology Trends

Index

Chapter 11. Software-Based Self-Testing

Jiun-Lang Huang
National Taiwan University, Taipei, Taiwan

Kwang-Ting (Tim) Cheng
University of California, Santa Barbara, California

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