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4.6. Exercises
| 4.1 | (SOC Test Infrastructure Design) Consider an embedded core, referred to as C in a core-based SOC. C has 8 functional inputs a[0:7], 11 functional outputs z[0:10], 9 internal scan chains of lengths 12, 12, 8, 8, 8, 6, 6, 6, and 6 flip-flops, respectively, and a scan enable control signal SE. The test wrapper for C is to be connected to a 4-bit TAM. Design the wrapper for this core, and present your results in the form of the following table for each wrapper scan chain n (1 to 4):
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| 4.2 | (SOC Test Infrastructure Design) Next consider the same embedded core C as in Exercise 4.1. The test wrapper for C is to be connected to two TAMs: a 4-bit TAM and a 6-bit TAM. Design a reconfigurable wrapper for this scenario, and compute the savings in test time (as a percentage) if a 6-bit-wide TAM is used. | ||||||||||||
| 4.3 | (NOC Infrastructure) Refer to the ITC-2002 SOC benchmarks [ITC 2002], and verify the data illustrated in Table 4.1 using the methodology introduced in Section 4.2. | ||||||||||||
| 4.4 | (NOC Test Scheduling) Using the system d695 shown in Figure 4.13 and data in Table 4.1, develop a nonpreemptive schedule for cores in system d695. Based on this result, assume all routers are identical and the test time of a router equals the average test time of embedded cores. Calculate the test time for testing all routers. | ||||||||||||
| 4.5 | (Integrated NOC Test Scheduling for Test Time Reduction) In the previous problem, what method can be used to reduce the test time of all routers in the NOC? What method can be used to reduce the overall test time of cores and routers? | ||||||||||||
| 4.6 | (NOC Test Using On-Chip Clocking) Now assume on-chip clocking scheme is used and the operation clock on NOC for testing is CLK. Also assume each core can be tested using CLK/2, CLK, or CLK*2 under certain constraints. Using the data shown in Table 4.1, design the wrapper architecture for each core in d695, and then upgrade your scheduling method for embedded cores (without consideration of routers) by incorporating these multiple clocks. Note that cores tested using slow clocks may share a physical channel in a time-multiplexing manner. Observe the test time, and compare it with the result you obtained in Problem 4.4. | ||||||||||||
| 4.7 | (NoC Interconnect Test Application)
Figure 4.22 shows an example for interleaved unicast MAF test of an NOC. Assume interconnects between each pair of routers are unidirectional (i.e., the wires for data transmission from router R1 to router R2 are different from those from router R2 to router R1). Find test configurations (paths) to apply the MAF test to all wires without any wire traveled redundantly. Show your answer by using a mesh with size M×N where M = 3, N = 4; M = 4, N = 4, and M = 5, N = 4. Note that M is the number of routers in the x direction, and N is the number of routers in the y direction.
To further simplify the analysis, you can replace each (bidirectional) interconnect in Figure 4.22 with two unidirectional interconnects, and assume there are only two unidirectional interconnects between each pair of routers. |
