Chapter 4. New and Changed Operations

In VHDL, we model computation by writing expressions that involve application of operations (operators and functions) to operand values. Each operand is of some type, either predefined or user-defined. VHDL defines overloaded versions of operations to perform computation on values of various types. In VHDL-2008, a number of new operations are introduced, and the variety of types to which existing operations can be applied is expanded. We describe the new and changed operations in this chapter.

One point to note is that in earlier versions of VHDL, many of the operations were defined in separate standards. In particular, IEEE Std 1164 specified the package std_logic_l164, which defined the types std_ulogic, stdjogic, std_ulogic_vector, and std_logic_vector and the operations on those types. Also, IEEE Std 1076.3 specified the packages numeric_bit and numeric_std, each of which defined the types unsigned and signed and operations on those types. All of these packages are now included as part of the VHDL-2008 standard. Other changes to the standard packages are described in Chapters 7 and 8.