9.4. Conclusions

The significant interest in MPSoC architectures in recent times has caused researchers to study architectural optimizations from a different perspective. With the full advance knowledge of the applications being implemented by the system, many design parameters can be optimized and/or customized. This is especially true of the memory subsystem, in which a vast array of different organizations can be employed for application-specific systems, and the designer is not restricted to the traditional cache hierarchy. The optimal memory architecture for an application-specific system can be significantly different from the typical cache hierarchy of processors. In this chapter, we outlined different memory architectures relevant to embedded systems and strategies to customize them for a given application. Although some of the analytical techniques can be automated, much work remains to be performed before a completely “push-button” methodology evolves for application-specific customization of the memory organization in MPSoCs. We also discussed the current compiler support available (from parallelism, locality, memory usage, and power/energy consumption perspectives) and pointed out potential research directions.