Chapter 7. VITAL Tables

One of the strengths of Verilog is its user-defined primitives. The VITAL standard brings similar capability to VHDL. VITAL tables can be used to model a variety of combinatorial and state-dependent behaviors.

In the early 1990s, the VITAL team was formed and tasked with finding a way to improve the gate-level simulation performance of VHDL so it could compete with Verilog. In performing this mandate, they were not shy about borrowing from Verilog’s strengths. One of the features they borrowed was Verilog’s UDPs. The UDP has been a useful tool for Verilog model writers since its inception because it gives the writer the ability to concisely define the behavior of small digital circuits such as gates, multiplexers, decoders, and counters. The result was VITAL truth tables and VITAL state tables. Truth tables and state tables are defined in the VITAL_Primitives package.