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Section A.1. Standards
A.1. Standards
The current standard of SystemVerilog is published by the IEEE and Accellera, an industry-based standards association. It is given the number 3.1a, which indicates that it is the third major revision of Verilog. These are the SystemVerilog and Verilog standards.
IEEE Standard 1800-2005/IEC 62530:2007
This is the LRM. This, however, only defines the extensions to the Verilog standard—1364-2005. To get a full definition of SystemVerilog, both LRMs are needed.
