9. SystemVerilog Simulation

SystemVerilog is a language for describing digital systems. To verify that a model is correct, a simulator may be used to animate the model. It is also important to remember that RTL synthesis attempts to generate low-level hardware that behaves in the same way as the original code. In other words, the interpretation of SystemVerilog structures for synthesis is based on the simulation model. In the first section of this chapter, the principles of digital simulation are described. The specifics of SystemVerilog simulation and techniques to improve simulation efficiency are then discussed.