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Chapter 2. Overview of Architecture and ... > MULTIPLE CHOICE QUESTIONS

MULTIPLE CHOICE QUESTIONS

  1. An 8048 port P2 signal has

    (a) address lower 8 bits

    (b) 8 data bits

    (c) Latched port bits

    (d) Either the address higher 8 bit or latched port bits

  2. 8048 accumulator (A-register)

    (a) Is an input during an ALU operation and accumulates the results from the ALU

    (b) Is an input during an ALU operation and accumulates along with the flags the results from the ALU

    (c) Accumulates the results from the ALU

    (d) Accumulates temporarily the A-register before an ALU operation

  3. , , and are the signals in 8048 (also in 8051). In this

    (a) , are not at the Port P3

    (b) , , and are at P3

    (c) all four are at P3

    (d) , and are at P3

  4. Classic 8051, extended 8051 and 8051MX have which of the following memory?

    (a) 64 kB external program ROM, 64 kB external data and 128 B internal RAMs, respectively

    (b) 64 kB program memory, 16 MB program plus constants memory and 64 MB program plus constants, respectively

    (c) 64 kB program memory, 16 MB program plus constants memory and 8 MB program plus 8 MB constants, respectively

    (d) 64 kB, 1 MB and 8 MB, respectively

  5. 68HC11/12/16 has

    (a) 4 kB and 64 kB internal/external common memory in unified address space, no separate program and data memory and 4 port plus ADC port

    (b) 64 kB, 1 MB and 4 MB common memory in unified address space, no separate program and data memory and 4 ports each

    (c) 64 kB, 1 MB and 4 MB memory with separate separate program and data memory and 4, 12 and 12 ports

    (d) 64 kB/4 MB/4 MB common memory in unified address space, no separate program and data memory and 4, 12, and 12 ports

  6. 8096 ALU can perform

    (a) 1 or 8 or 16-bit operations

    (b) 16-bit operations

    (c) 8 or 16 or 32 bit operations

    (d) 8 or 16-bit operations only

  7. An MCU has a port P2 and 64 kB external data memory. Ports P0, P1 and P3 are not usable in an expanded mode. The total external memory space now available is

    (a) 65,536 B

    (b) 64,000 B

    (c) 65,472 B

    (d) 63,036 byte

  8. A port must have.

    (a) One handshaking signal to request data input and one for acknowledgement after data input

    (b) One handshaking signal to request data input and one for acknowledgement after data input and one handshaking signal to convey buffer full and one for acknowledgement after data output successful on two common or four separate pins

    (c) O ne handshaking signal to convey buffer full and one for acknowledgement after data output successful on two common or four separate pins

    (d) Data direction register

  9. An MCU does not have bit-manipulation instructions and only the byte operations are feasible. To reset the bit 0 and bit 7, the following operations are needed when all the bits were 1s earlier:

    (a) AND with 1000 0001

    (b) XOR with 1000 0001

    (c) XOR with 1111 1111

    (d) OR with 1000 0001

  10. EEPROM

    (a) Is flash also

    (b) Is for erase at a time of one byte and flash for a sector of bytes

    (c) Is different from flash

    (d) Works identically for erase as well as write

  11. A pulse width modulator gives an output pulse width of n1% and after the integrator circuit gives 2 V when the pulse accumulator loads 0x40 (= 40H). It gives the width n2% and –2 V when the pulse accumulator loads 0x80 (= 80H). The n1 and n2 are

    (a) 0 and 50

    (b) -2/25 and +2/25

    (c) 50 and 100

    (d) 25 and 75

  12. A single reference input ADC operated on 5 V power supply input to its circuit and gives an output of 0000 1000. When input is 50 mV and 0000 1001 when input is 56.25 mV. It can measure maximum

    (a) 1.6 V

    (b) 3.2 V

    (c) 5V

    (d) Maximum cannot be determined with this information alone

  13. An 8-bit auto-reload timer is loaded to an initial value of 40. It is given an input at the start of a race from a clock of 8 MHz after pre-scaling by a factor of 64. Now, the timer will overflow (timeout) in

    (a) (256 – 40) μs

    (b) Every (40/64) μs

    (c) Every (256 – 40)/8 μs

    (d) (40/8) μs

  14. A byte 1001 1110 is sent on an asynchronous UART in 10T periods where T determines from the baud rate of 9600. For how much minimum interval from the first start transition will there be 1s when this byte is sent twice successively with a gap of 100 ms.

    (a) (12 × 104 + 100) μs

    (b) (11 × 104 + 100) μs

    (c) (10 × 104 + 100) μs

    (d) (16 × 104 + 100) μs

  15. A watchdog timer is loaded 2048 in 8051 operating at 12 MHZ. It is reloaded when the program was running after 1000 μs. Watchdog timer will reset the MCU in.

    (a) 4096 μs

    (b) Cannot reset when reloaded

    (c) 1000 μs

    (d) 3048 μs

  16. A free-running counter is driven by 16 μs period inputs. On the start of a race, its content was captured and the input capture register showed 16,384 (= 0100 0000 0000 0000). At the stop of the race its contents were captured again and showed 65,530 (= 1111 1111 1111 1010). The race period is given by

    (a) 16 × (65,530 – 16,384) μs

    (b) 16 × [(65,530 – 16,384) + 65,536 × n] μs

    (c) 16 × [(65,536 – 16,384 + 65,530) + 65,536 × n] μs

    (d) 16 × n × (65,530 – 16,384) μs,

    where n is the number of times it overflows after the first overflow.


  

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