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Chapter 8. Input/Output Organization > 8.10 STANDARD I/O INTERFACES (BUSES)

8.10 STANDARD I/O INTERFACES (BUSES)

From the discussions so far, the reader must have understood that the input/output system for a computer are accommodated in many layers, like memory devices. We have already discussed about cache memory and a special high speed bus to communicate with it, designated as cache bus (Figure 8.13). Main memory of the system is also interfaced with the processor with a dedicated memory bus so that delay in I/O operations, which is quite normal and happens frequently, does not retard the instruction that has to be carried out.

The innermost layer of I/O devices is directly interfaced with the processor through its address, data and control bus (designated as I/O bus), and communicates in synchronous manner (synchronous parallel communication). Note that although with processor these devices communicate in synchronous fashion, with the external world they communicate in asynchronous manner. Example of I/O devices of this layer may be 8255-based ports, timers/counters for real-time operations, USART for serial communication and other similar devices. Note that 8255 communicates with its processor in synchronous manner while it functions asynchronously with the external world.


  

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