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Chapter 12. Pipelining > 12.5 INSTRUCTION HAZARDS

12.5 INSTRUCTION HAZARDS

The case of instruction hazard arises when the appropriate instruction does not become available to the processor at the required time, due to some reason or other. The reason behind this phenomenon varies widely and here we consider two major reasons behind this, namely cache-miss and conditional branching.

12.5.1 Cache-miss

Cache-hit means the required instruction (or data) is (are) presently available within the cache memory of the processor. On the other hand, cache-miss means that it is not available. If the required instruction is not available with the cache memory, the processor has to spend some extra time to fetch it from main memory, which was discussed in Chapter 7. However, this need for extra time for instruction fetch forces the pipeline to stall, which is one of the reasons behind instruction hazards. In modern processor, this problem is eliminated by providing an instruction queue of n-instructions. Whenever the fetch-unit is free and the queue offers some space, the fetch-unit grabs an instruction from outside (generally, from cache) and stores within the instruction queue. Note that this instruction queue is a part of the processor and, therefore, located physically inside the processor. Therefore, the cache-miss does not matter, in this case, as several instructions are already available within the instruction queue. As a matter of fact, this instruction queue is considered as an integral part of pipeline architecture. The queue is operated in FIFO or first in first out basis.


  

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