These have n inputs and m outputs. For examples, (i) A NOT (inverter) gate, n = 1 and m = 1. (ii) An XOR gate, n = 2 and m = 2. (iii) An 8-bit adder, which accepts in its inputs a carry bit, 8 bits of X and 8 bits of Y and results at outputs the 8 bit sum Z and final carry CY, n = 17 and m = 9.

Logic state, at any of the outputs in the combinational circuits, depends only on the inputs at any given instant (not considering always present propagation delay period) and is not correlated at all with any of its previous outputs or outputs.

A truth table of a combinational circuit gives the values of all the m outputs for each possible combination of the n inputs and has 2ⁿ rows and (n + m) columns.

A combination circuit can be designed for obtaining the m outputs using the m Boolean expressions.

Each expression can be represented by SOP or POS format. A Karnaugh map-based technique or computer-based minimization technique is used to get least cost (minimum number of gates) or least delay (minimum number of levels between inputs and the corresponding output).