Design a PIPO, which is a 4-bit buffer register with parallel in (loading) and parallel output (storing). [Hint: refer figure 16.2(a), use the AND buffers at both the ends.]

Show the state diagram from a state table corresponding to a SIPO. (Hint: Refer sate table at Table 16.2).

Design a multipurpose behavior of a left shift register, which shift left when channel inputs, are 01 and circularly shift left when 10, synchronous clear when 11 and no-shift when 00. (Hint: Refer Example 16.8).

Solve the problem in Example 16.2 once again for a left-shift register.

Design a SISO circular left shift register.

Draw and compare the state diagrams of (i) a SIPO of 4 bits (ii) a 4-stage ripple counter.

Give a state table and state diagram of a binary synchronous counter.

Give a state table and state diagram of a asynchronous down modulo 6 counter.

How much is the time interval for Qs to stabilize in a sixteen bit asynchronous counter? Assume flip flop propagation delays = 10 ns.

How will you make circuit of modulo-7 counter?

Show state diagram of a modulo-4 counter?

What should be the count value for a 8-bit counter to time out in 1 ms if input clock pulses at 100 ms intervals?

Show the timing diagram of a ring counter.

Show the circuit of a 3-bit Johnson counter.

Show the timing diagram of a Johnson counter modified for maximum 7-sequence clock generator.