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PROBLEMS

1:We have a hardware pipeline that takes 200 logic gates to construct. We assume that processing a signal through a logic gate takes one unit of time. Our processor architect is proposing to split the pipeline in two to aid parallelism of instructions. To do so will require 30 additional logic gates to “glue” the two hardware pipelines together. We have an instruction stream of 100 instructions. What will be the overall speedup of pipelining this architecture?
2:Is a unified cache architecture an advantage or disadvantage to a pipeline processor architecture?
3:If my application accesses data elements in a sequential fashion, i.e., one after another, would it be better to have a “long” (holding lots of data elements) or “short” (holding fewer data elements) cache line?
4:Give another name to a one-way set associative cache.
5:I am using Set Associative Mapping for my cache architecture. I am using 2 bits to encode the “set number” of the cache lines able to store my datum. I want to employ four-way Set Associative mapping. What is the minimum number of cache lines I need to employ to achieve this?


  

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