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General Topics > Using Large DTLB Page Sizes
Using Large DTLB Page Sizes
Darryl Gove, April 18, 2007
The TLB is a structure on the chip that handles the mapping of virtual memory addresses (used by the application) into physical memory addresses (used by the hardware). It is a list of such mappings, with each mapping describing a range of memory (called the page size). The default on SPARC is 8KB page sizes, but it can be configured up to impressively large sizes (for example, 256MB for UltraSPARC T1). The command to display what page sizes the hardware supports is pagesize(1):
