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Cache Thrash

One of the interesting effects of having a cache in a multiprocessor system is the effect of cache coherency protocols on cache performance. A cache coherency protocol is a mechanism employed by memory/cache controllers that maintains a coherent view of memory across a number of what would otherwise be unassociated caches. The problem is simple: processor A wants to write to memory location 100 and processor B wants to read from memory location 100. If B has previously read from location 100 and has a copy of it in its cache then another read will not go out onto the system bus to refetch it. This is the behavior you want if the processor is to go fast. However, if processor A has written a new value to location 100 between the time B read that location the first time and the time B read it for the second time, then without a coherency protocol, processor B will read the stale (old, incorrect) contents of location 100, not the fresh (new, correct) content.

Cache coherency protocols are based on notions of memory ownership and explicit invalidation of peer cache entries on reads. This basically amounts to a protocol that allows multiple caches to share a copy of a single data item, but only one cache to have write privileges for the data item at a time. If the owner (the one with write access) is not actively updating the data, then other caches can have their own copy of the cache line, but every time the owner of the cache line modifies the line, it tells all other caches to invalidate their copy. Invalidating the other copies will force the other caches to get another copy before they read it again. This will allow the owning cache to supply its peer caches with what is now the only correct value for the cache line. At some point the cache line will be flushed out to memory, maintaining the overall consistency of the memory system.


  

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