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Chapter 4: Introduction to the Thumb Ins... > 4.5 Single-Register Load-Store Instr...

4.5 SINGLE-REGISTER LOAD-STORE INSTRUCTIONS

The Thumb instruction set supports load and storing registers, or LDR and STR. These instructions use two preindexed addressing modes: offset by register and offset by immediate.

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You can see the different addressing modes in Table 4.3. The offset by register uses a base register Rn plus the register offset Rm. The second uses the same base register Rn plus a 5-bit immediate or a value dependent on the data size. The 5-bit offset encoded in the instruction is multiplied by one for byte accesses, two for 16-bit accesses, and four for 32-bit accesses.

Table 4.3 Addressing modes.

Type Syntax
Load/store register [Rn, Rm]
Base register + offset [Rn, # immediate]
Relative [pc|sp, #immediate]

  

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